HC4GX15 Datasheet, PDF (11/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1. HardCopy IV Device Family Overview
HIV51001-2.2
This chapter provides an overview of features available in the HardCopy IV device
family. More details about these features can be found in their respective chapters.
HardCopy^® IV ASICs are the only 40-nm system-capable ASICs designed with an
FPGA design flow. Altera's fifth generation of HardCopy IV ASICs deliver low-cost
and high-performance at low-power. Based on a 0.9-V, 40-nm process, the
HardCopy IV family is supported by Stratix IV FPGAs, which have complementary
pin-outs, densities, and architectures that deliver in-system, at-speed prototyping—
resulting in first-time-right ASICs. The Quartus^® II software provides a complete set
of tools for designing the Stratix IV FPGA prototypes and HardCopy IV ASICs. One
design, one RTL, one set of intellectual property, and one tool deliver both ASIC and
FPGA implementations. Other front-end design tools from Synopsys and Mentor
Graphics^® are also supported.
To reduce risk, HardCopy IV device features, such as phase-locked loops (PLLs),
embedded memory, transceivers, and I/O elements (IOEs), are functionally and
electrically equivalent to the Stratix IV FPGA features. To reduce cost, Altera^®
HardCopy IV devices are customized using only two metal and two via layers. The
combination of the Quartus^® II software for design, Stratix IV FPGAs for in-system
prototype and design verification, and HardCopy IV devices for high-volume
production provides the fastest time to market, lowest total cost, and lowest risk
system design and production solution to meet your business needs.
The HardCopy IV device family contains two variants optimized to meet different
application needs:
■ HardCopy IV GX transceiver ASICs—up to 11.5 M usable ASIC equivalent gates,
20,736 Kbits dedicated RAM, 1,288 18 × 18-bit multipliers, and 36 full-duplex clock
data recovery (CDR)-based transceivers at up to 6.5 Gbps
■ HardCopy IV E ASICs—up to 14.6 M usable ASIC equivalent gates, 18,792 Kbits
dedicated RAM, and 1,288 18 × 18 bit multipliers
This chapter contains the following sections:
■ “Features” on page 1–2
■ “Architectural Features” on page 1–10
■ “Software Support and Part Number Information” on page 1–15
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1