HC4GX15 Datasheet, PDF (145/668 Pages) Altera Corporation – HardCopy IV Device Handbook

10. IEEE 1149.1 (JTAG) Boundary Scan
Testing in HardCopy IV Devices
HIV51010-2.0
All HardCopy^® IV ASICs provide Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry that complies with the IEEE Std. 1149.1 specification. The BST
architecture offers the capability to efficiently test components on PCBs with tight
lead spacing. Pin connections can be tested without using physical test probes, and
functional data can be captured while a device is in normal operation. Boundary-scan
cells in a device can force signals onto pins, or capture data from pin or core logic
signals. Forced test data is serially shifted into the boundary-scan cells. Captured data
is serially shifted out and externally compared to expected results.
A device using the JTAG interface uses four required pins: TDI, TDO, TMS, and TCK,
and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, and
the TDI, TMS, and TRST pins have internal weak pull-up resistors. The TDO output pin
and all the JTAG input pins are powered by the 2.5-V/3.0-V V_CCPD supply of I/O
bank 1A.
f For more information about the JTAG pin description, refer to the JTAG Boundary-Scan
Testing in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.
JTAG Instructions
Table 10–1 shows the JTAG instructions supported in HardCopy IV devices for
boundary-scan testing (BST). These 10-bit instructions are also supported in Stratix IV
devices. However, HardCopy IV devices do not support the Stratix IV JTAG
instructions used for in-circuit reconfiguration (ICR), because HardCopy IV devices
do not require configuration.
f For more information about the BST architecture and JTAG instructions supported in
Stratix IV devices, refer to the JTAG Boundary-Scan Testing in Stratix IV Devices chapter
in volume 1 of the Stratix IV Device Handbook.
Table 10–1. HardCopy IV JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
EXTEST (1)
BYPASS
USERCODE
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern to be output at the device pins.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
Loads the 32-bit user code into the device identification register and
places the register between the TDI and TDO pins, allowing the user
code to be serially shifted out of TDO.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 1