HC4GX15 Datasheet, PDF (62/668 Pages) Altera Corporation – HardCopy IV Device Handbook

6–12
Chapter 6: HardCopy IV Device I/O Features
External Memory Interfaces
■ Output current strength
■ Slew rate control
■ Output buffer delay
■ Open-drain output
■ Bus hold
■ Pull-up resistor
f For more information about particular features, refer to the I/O Features in Stratix IV
Devices chapter in volume 1 of the Stratix IV Device Handbook.
External Memory Interfaces
In addition to the I/O registers in each IOE, HardCopy IV devices also have dedicated
registers and phase-shift circuitry on all I/O banks for interfacing with external
memory interfaces.
f For more information about external memory interfaces, refer to the External Memory
Interfaces chapter.
High-Speed Differential I/O with DPA Support
HardCopy IV devices have the following dedicated circuitry for high-speed
differential I/O support:
■ Differential I/O buffer
■ Transmitter serializer
■ Receiver deserializer
■ Data realignment
■ Dynamic phase aligner
■ Synchronizer (FIFO buffer)
■ Phase-locked loops (PLLs)
f For more information about DPA support, refer to the High-Speed Differential I/O
Interfaces with DPA chapter.
On-Chip Termination Support and I/O Termination Schemes
HardCopy IV devices support the same termination schemes and on-chip termination
(OCT) architecture as Stratix IV devices. I/O termination provides impedance
matching and helps maintain signal integrity while on-chip termination saves board
space and reduces external component costs.
HardCopy IV devices support on-chip series termination (R_S) with or without
calibration, parallel (R_T) with calibration, dynamic series and parallel termination for
single-ended I/O standards, and on-chip differential termination (R_D) for differential
LVDS I/O standards.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation