HC4GX15 Datasheet, PDF (456/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–192
Chapter 1: HardCopy IV GX Transceiver Architecture
Calibration Blocks
In Figure 1–160, the grayed areas show the inactive paths when the PCI Express
(PIPE) reverse parallel loopback mode is enabled.
Figure 1–160. PCI Express (PIPE) Reverse Parallel Loopback Mode Datapath (Grayed-Out Blocks are Not Active in this
Mode)
PCI
Express
hardIP
PIPE
Interface
TX Phase
Compensation
FIFO
Transmitter Channel PCS
Byte
Serializer
8B/10B
Encoder
Transmitter Channel PMA
Serializer
Core
Fabric
PCI
Express
hardIP
PIPE
Interface
RX Phase
Compen-
sation FIFO
Reverse Parallel
Loopback Path
Receiver Channel PCS
Receiver Channel PMA
Byte
De-
Serializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
De-
Serializer
CDR
Calibration Blocks
HardCopy IV GX devices contain calibration circuits that calibrate the OCT resistors
and the analog portions of the transceiver blocks to ensure that the functionality is
independent of process, voltage, or temperature variations.
Calibration Block Location
Figure 1–161 shows the location and number of calibration blocks available for
different transceiver block device families. In Figure 1–161 through Figure 1–163, the
calibration block R0 and L0 refer to the calibration blocks on the right and left side,
respectively.
Figure 1–161. Calibration Blocks
GXBL1
GXBR1
GXBL0
HardCopy IV GX
Device
GXBR0
Calibration
Block L0
2K Ω
Calibration
Block R0
2K Ω
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation