HC4GX15 Datasheet, PDF (601/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Dynamic Reconfiguration Duration and Core Fabric Resource Utilization
2–143
Assume that you create another instance with the following configuration:
■ ALTGX Instance 2: one channel with a Receiver and Transmitter configuration,
with only one transmitter PLL (assume a logical tx pll value of 0), configured to
6.25 Gbps.
In this case, you cannot merge ALTGX instance 1 and ALTGX instance 2 in the same
transceiver bank because ALTGX instance 2 listens to only one transmitter PLL. To
successfully merge the two instances, create ALTGX instance 2 with an alternate
transmitter PLL configured to 2.500 Gbps.
Merging Transceiver Channels Listening to One Transmitter PLL
Consider that you create an ALTGX instance (Receiver and Transmitter or
Transmitter Only configuration) that has only one transmitter PLL. If you want to
create another ALTGX instance configured at a different data rate in the same
transceiver bank, provide different logical tx pll values for the two instantiations.
For example, to merge the following instantiations in the same transceiver bank:
■ ALTGX Instance 1: one channel with a Receiver and Transmitter configuration,
configured at 3.125 Gbps data rate.
■ ALTGX Instance 2: one channel with a Receiver and Transmitter configuration,
configured at 2.500 Gbps. If you set the What is the main transmitter PLL logical
reference index? option (in the Reconfig Clks screen) for ALTGX instance 1 to 0,
set this option to 1 for ALTGX instance 2. The two ALTGX instances need to have
different logical tx pll values because the Quartus II software requires separate
transmitter PLLs for these two channels.
Dynamic Reconfiguration Duration and Core Fabric Resource Utilization
This section describes the time taken for dynamic reconfiguration transactions and
core fabric resources used by the dynamic reconfiguration controller when used in
different modes of reconfiguration.
Dynamic Reconfiguration Duration
Dynamic reconfiguration duration is the number of cycles for which the busy signal
is asserted when the dynamic reconfiguration controller performs write transactions,
read transactions, or offset cancellation of the receiver channels.
PMA Controls Reconfiguration Duration
The following section contains an estimate of the number of reconfig_clk clock
cycles for which the busy signal is asserted during PMA controls reconfiguration
using Method 1 and Method 2. For more information, refer to “Dynamically
Reconfiguring PMA Controls” on page 2–53.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3