HC4GX15 Datasheet, PDF (320/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Transmitter Channel Datapath
The following protocols supported by HardCopy IV GX devices mandate
AC-coupled links:
■ PCI Express (PIPE)
■ Gigabit Ethernet
■ Serial RapidIO
■ XAUI
■ SDI
DC-Coupled Links
In a DC-coupled link, the transmitter DC common mode voltage is seen unblocked at
the receiver buffer. The link common mode voltage depends on the transmitter
common mode voltage and the receiver common mode voltage. The on-chip or
off-chip receiver termination and biasing circuitry must ensure compatibility between
the transmitter and the receiver common mode voltage. Figure 1–44 shows a
DC-coupled link.
Figure 1–44. DC-Coupled Link
Transmitter
Receiver
Physical Medium
TX Termination
Physical Medium
RX Termination
TX
RX
V_CM
V_CM
The HardCopy IV GX transmitter can be DC-coupled to a HardCopy IV GX receiver
for the entire operating data rate range of HardCopy IV GX devices, from 600 Mbps to
6.5 Gbps.
PCI Express (PIPE) Receiver Detect
The HardCopy IV GX transmitter buffer has a built-in receiver detection circuit for
use in the PIPE mode for Gen1 and Gen2 data rates. This circuit detects if there is a
receiver downstream by sending out a pulse on the common mode of the transmitter
and monitoring the reflection. This mode requires the transmitter buffer to be
tri-stated (in Electrical Idle mode), OCT utilization, and a 125 MHz fixedclk signal.
You can enable this feature in PIPE mode by setting the tx_forceelecidle and
tx_detectrxloopback ports to 1'b1. Receiver detect circuitry is active only in the
P1 power state.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation