HC4GX15 Datasheet, PDF (297/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–33
Auxiliary Transmit (ATX) PLL Block
Input Reference Clocks for the ATX PLL
The ATX PLL block does not have a dedicated reference clock pin. The following are
the possible input reference clock sources:
■ REFCLKS from the transceiver blocks on the same side of the device, if the
corresponding CMU channels are not used as transceiver channels
■ Input reference clock provided through the PLL cascade clock network
■ Clock inputs connected through the global clock lines
Altera recommends that you use the REFCLK pins from the adjacent transceiver block
below the ATX PLL block to improve performance.
Architecture of the ATX PLL Block
The ATX PLL block contains the ATX PLL, ATX clock divider, and a shared control
signal generation block, as shown in Figure 1–17.
Figure 1–17. ATX PLL Block
pll_powerdown
ATX PLL
high-speed
Clock (1)
ATX PLL Block
cascaded PLL clock
global clock line
ITB clock lines
8
PCIErateswitch
ATX PLL input
reference clock
ATX PLL
ATX clock
divider block
high-speed serial clock
for bonded modes (2)
PCIE_gen2switch
PCI Express
rateswitch
controller
PCIE_gen2switch_done
Notes to Figure 1–17:
(1) In non-bonded functional modes (for example, CEI functional mode), the transmitter channel uses the transmitter local clock divider to divide this
high-speed clock output to provide clocks for its PMA and PCS blocks.
(2) This is used in Basic ×4, ×8, and PCI Express (PIPE) ×4 and ×8 functional modes.
The functional blocks on the ATX PLL are similar to the blocks explained in “CMU0
PLL” on page 1–24. The values of the /M and /L divider settings in the ATX PLL are
automatically selected by the Quartus II software based on the transceiver channel
configuration.
The ATX PLL high-speed clock output provides high-speed serial clocks for
non-bonded functional modes such as CEI (with the subprotocol “none”).
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3