HC4GX15 Datasheet, PDF (335/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–71
Receiver Channel Datapath
LTR/LTD Controller
The LTR/LTD controller controls whether the CDR is in LTR or LTD mode. You can
configure the LTR/LTD controller either in automatic lock mode or manual lock
mode.
Two optional input ports (rx_locktorefclk and rx_locktodata) allow you to
configure the LTR/LTD controller in either automatic lock mode or manual lock
mode. Table 1–18 shows the relationship between these optional input ports and the
LTR/LTD controller lock mode.
Table 1–18. Optional Input Ports and LTR/LTD Controller Lock Mode
rx_locktorefclk
1
x
0
rx_locktodata
0
1
0
LTR/LTD Controller Lock Mode
Manual – LTR Mode
Manual – LTD Mode
Automatic Lock Mode
1 If you do not instantiate the optional rx_locktorefclk and rx_locktodata
signals, the Quartus II software automatically configures the LTR/LTD controller in
automatic lock mode.
Automatic Lock Mode
In automatic lock mode, the LTR/LTD controller initially sets the CDR to lock to the
input reference clock (LTR mode). After the CDR locks to the input reference clock,
the LTR/LTD controller automatically sets it to lock to the incoming serial data (LTD
mode) when the following three conditions are met:
■ Signal threshold detection circuitry indicates the presence of valid signal levels at
the receiver input buffer
■ The CDR output clock is within the configured PPM frequency threshold setting
with respect to the input reference clock (frequency locked)
■ The CDR output clock and the input reference clock are phase matched within
approximately 0.08 UI (phase locked)
The switch from LTR to LTD mode is indicated by the assertion of the
rx_freqlocked signal.
In LTD mode, the CDR uses a phase detector to keep the recovered clock
phase-matched to the data. If the CDR does not stay locked to data due to frequency
drift or severe amplitude attenuation, the LTR/LTD controller switches the CDR back
to LTR mode to lock to the input reference clock. In automatic lock mode, the
LTR/LTD controller switches the CDR from LTD to LTR mode when the following
conditions are met:
■ Signal threshold detection circuitry indicates the absence of valid signal levels at
the receiver input buffer
■ The CDR output clock is not within the configured PPM frequency threshold
setting with respect to the input reference clock
The switch from LTD to LTR mode is indicated by the de-assertion of the
rx_freqlocked signal.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3