HC4GX15 Datasheet, PDF (592/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–134
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Design Examples: Dynamic Reconfiguration Controller
Table 2–38. Step 1: Generate the ALTGX Instance for the GIGE Configuration (Part 2 of 3)
ALTGX MegaWizard Plug-In
Manager Option
PLL/Ports screen
In the Optional Ports section:
Reconfig Screen
Analog Controls (VOD,
Pre-emphasis, and Manual
Equalization) option
Enable Channel and Transmitter
PLL Reconfiguration option
Channel Interface option
Use alternate Transmitter PLL
option
What is the protocol to be
reconfigured to? option
What is the subprotocol to be
reconfigured to? option
What is the input clock
frequency? and What is the
alternate Transmitter PLL
bandwidth mode? options
Setting
Select the following control and status signals:
■ rx_digitalreset
■ tx_digitalreset
■ rx_analogreset
■ rx_pll_locked
■ rx_freqlocked
Add the other required status signals (For a list of ALTGX
signals and their functionality, refer to the Transceiver Port
List in the HardCopy IV GX Transceiver Architecture chapter in
volume 3 of the HardCopy IV Device Handbook.)
If you need control of the transceiver PMA controls, select
Analog PMA controls. For more information about PMA
controls, refer to “PMA Controls Reconfiguration” on
page 2–52.
Because you need to reconfigure the transceiver channel from
a GIGE configuration to a SONET/SDH OC48 configuration,
select this option.
Selecting this option creates the data interface signals
tx_datainfull[43:0] and
rx_dataoutfull[63:0] that are comprised of control
and data signals. This selection is required because the core
fabric-Transceiver Interface is different for a GIGE
configuration versus a SONET/SDH configuration (Refer to
row 8 in Table 2–37 on page 2–131). The description of the
individual bits of tx_datainfull[43:0] and
rx_datainfull[63:0] are provided in Table 2–28 on
page 2–91 and Table 2–29 on page 2–94.
Selecting this option enables the second PLL for the
SONET/SDH OC48 configuration. A second PLL is needed
because of the difference in the required input clock
frequency and data rate between the GIGE and SONET/SDH
OC48 configurations (Refer to rows 6 and 7 in Table 2–37 on
page 2–131).
Set this option to SONET/SDH.
Set sub protocol to OC48.
Select the input clock frequency and alternate transmitter
PLL bandwidth mode options based on the requirements.
The allowed reference clock input frequencies for
SONET/SDH OC48 are specified in row 7 of Table 2–37 on
page 2–131.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation