HC4GX15 Datasheet, PDF (341/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Figure 1–61. Word Aligner Configured in Bit-Slip Mode
n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14
rx_clkout
rx_datain
11110000
rx_dataout[7:0]
rx_bitslip
11110000
01111000
00111100
00011110
00001111
rx_patterndetect
1–77
Word Aligner in Single-Width Mode with 10-Bit PMA-PCS Interface Modes
The following functional modes support the 10-bit PMA-PCS interface:
■ PCI Express (PIPE) Gen1 and Gen2
■ Serial RapidIO
■ XAUI
■ GIGE
■ SDI
■ Basic single-width mode
This section describes the following word aligner 10-bit PMA-PCS interface modes:
■ Automatic synchronization state machine mode with 10-bit PMA-PCS interface
mode
■ Manual alignment mode with 10-bit PMA-PCS interface mode
■ Bit-slip mode in 10-bit PMA-PCS interface mode
Table 1–20 shows the word aligner configurations allowed in functional modes with a
10-bit PMA-PCS interface.
Table 1–20. Word Aligner Configurations with a 10-Bit PMA-PCS Interface
Functional Mode
PCI Express (PIPE)
Serial RapidIO
XAUI
GIGE
SDI
Basic single-width
mode
Allowed Word Aligner Configurations
Automatic synchronization state machine
Automatic synchronization state machine
Automatic synchronization state machine
Automatic synchronization state machine
Bit-slip
Manual Alignment, Automatic
synchronization state machine, Bit-slip
Allowed Word Alignment
Pattern Length
10 bits
10 bits
7 bits, 10 bits
7 bits, 10 bits
N/A
7 bits, 10 bits
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3