HC4GX15 Datasheet, PDF (545/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Figure 2–44. Receiver Core Clocking for Option 3
ASIC Core
Transceiver Block
rx_clkout[0]
TX0 (2 Gbps)
RX0
rx_clkout[1]
TX1 (2 Gbps)
RX3
rx_clkout[2]
TX2 (2 Gbps)
RX2
rx_clkout[3]
TX3 (2 Gbps)
RX3
High-speed serial clock generated by the CMU0 PLL
High-speed serial clock generated by the CMU1 PLL
2–87
CMU1 PLL
CMU0 PLL
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3