HC4GX15 Datasheet, PDF (198/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–2
Chapter 2: HardCopy Design Center Implementation Process
HardCopy IV Back-End Design Flow
Design for Testability
The HardCopy Design Center inserts the necessary test structures into the
HardCopy IV Verilog netlist. These test structures include full-scan capable registers
and scan chains, JTAG, and memory testing. After adding the test structures, the
modified netlist is verified using third-party EDA formal verification software against
the original Verilog netlist to ensure that the test structures have not broken your
netlist functionality. “Formal Verification of the Processed Netlist” on page 2–2
explains the formal verification process.
Clock Tree and Global Signal Insertion
Along with test insertion, the HardCopy Design Center adds a local layer of clock tree
buffering to connect the global clock resources to the locally placed registers in the
design. Global signals with high fan-out can also use dedicated global clock resources
built into the base layers of all HardCopy IV devices. The HardCopy Design Center
does local buffering.
Tie-Off Connections for Unused Resources
If an unused resource in a customer design still exists in the HardCopy IV database,
the HardCopy Design Center uses special handling on the tie-off connections for
these resources. I/O ports of unused resources are connected to power or ground so
that the resources are in a lower power state. This is achieved by using the same metal
layers that are used to configure and connect all resources used in the design.
Formal Verification of the Processed Netlist
After all design-for-testability logic, clock tree buffering, global signal buffering, and
tie-off connection are added to the processed netlist, the HardCopy Design Center
uses third-party EDA formal verification software to compare the processed netlist
with your submitted Verilog netlist generated by the Quartus II software. Added test
structures are constrained to bypass mode during formal verification to verify that
your design’s intended functionality is unchanged.
Timing and Signal Integrity Driven Place and Route
Placement and global signal routing is principally done in the Quartus II software
before submitting the HardCopy IV design to the HardCopy Design Center. With the
Quartus II software, you control the placement and timing driven placement
optimization of your design. The Quartus II software also does global routing of your
signal nets, and passes this information in the design database to the HardCopy
Design Center to do the final routing. After the design is submitted, Altera engineers
use the placement and global routing information provided in the design database to
do final routing and timing closure, and to perform signal integrity and crosstalk
analysis. This may require buffer and delay cell insertion in the design through an
engineering change order (ECO). The resulting post place and route netlist is verified
again with the source netlist and the processed netlist to guarantee that functionality
was not altered in the process. For more details about back-end timing closure and
timing ECOs, refer to “Back-End Timing Closure” and “Timing ECOs”.
HardCopy IV Device Handbook, Volume 2
© December 2008 Altera Corporation