HC4GX15 Datasheet, PDF (22/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV Device Family Overview
Architectural Features
Clock Networks and PLLs
HardCopy IV devices provide dedicated global clock networks (GCLKs), regional
clock networks (RCLKs), and periphery clock networks (PCLKs). These clocks are
organized into a hierarchical clock structure that provides up to 192 unique clock
domains (16 GCLK + 88 RCLK + 88 PCLK) within the HardCopy IV device and allows
up to 60 unique GCLK/RCLK/PCLK clock sources (16 GCLK + 22 RCLK + 22 PCLK)
per device quadrant.
HardCopy IV devices deliver abundant PLL resources, with up to 12 PLLs per device
and up to 10 outputs per PLL. You can configure each output independently, creating
a unique, customizable clock frequency with no fixed relation to any other input or
output clock. Inherent jitter filtration and fine granularity control over multiply,
divide ratios, and dynamic phase-shift reconfiguration provide the high-performance
precision required in today’s high-speed applications. HardCopy IV PLLs are
feature-rich, supporting advanced capabilities such as clock switchover,
reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. You
can use PLLs for general-purpose clock management, supporting multiplication,
phase shifting, and programmable duty cycles. HardCopy IV PLLs also support
external feedback mode, spread-spectrum input clock tracking, and post-scale counter
cascading.
f For more information about clock networks and PLLs, refer to the Clock Networks and
PLLs in HardCopy IV Devices chapter in volume 1 of the HardCopy IV Device Handbook.
I/O Banks and I/O Structure
HardCopy IV devices contain up to 20 modular I/O banks, each containing 24, 32, 40,
or 48 I/Os (not including dedicated clock inputs). The left- and right-side I/O banks
contain circuitry to support external memory interfaces and high-speed differential
I/O interfaces capable of performance at up to 1.25 Gbps. The top and bottom I/O
banks also contain circuitry to support external memory interfaces.
HardCopy IV devices support a wide range of industry I/O standards, including
single-ended, voltage referenced single-ended, and differential I/O standards. The
HardCopy IV I/O supports bus hold, pull-up resistor, slew rate, output delay control,
and open-drain output. HardCopy IV devices also support on-chip series (R_S) and
on-chip parallel (R_T) termination with auto calibration for single-ended I/O
standards. The left and right I/O banks support on-chip differential termination (R_D)
to meet LVDS I/O standards. Bidirectional I/O pins on all I/O banks also support
Dynamic OCT.
f For more information about I/O features, refer to the HardCopy IV Device I/O Features
chapter in volume 1 of the HardCopy IV Device Handbook.
External Memory Interfaces
The HardCopy IV I/O structure is equivalent to the Stratix IV I/O structure,
providing high-performance support for existing and emerging external memory
standards such as DDR, DDR2, DDR3, QDRII, QDRII+, and RLDRAM II.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation