HC4GX15 Datasheet, PDF (299/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–35
Transceiver Channel Architecture
■ Receiver channel, further divided into
■ Receiver channel PCS
■ Receiver channel PMA
Each transceiver channel interfaces to either the PCI Express (PIPE) hard IP block
(PIPE hard IP-transceiver interface) or directly to the core fabric (core fabric—
transceiver interface). The transceiver channel interfaces to the PIPE hard IP block if
the hard IP block is used to implement the PCI Express PHY MAC, data link layer,
and transaction layer. Otherwise, the transceiver channel interfaces directly to the core
fabric.
1 The PIPE hard IP—transceiver interface is out of the scope of this chapter. This
chapter describes the core fabric-transceiver interface.
f For more information about the PCI Express (PIPE) hard IP block, refer to the PCI
Express Compiler User Guide.
Figure 1–20 shows the core fabric-transceiver interface and transceiver PMA-PCS
interface.
Figure 1–20. Core Fabric-Transceiver Interface and Transceiver PMA-PCS Interface
Core Fabric-
Transceiver Interface
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
PMA-PCS
Interface
Transmitter Channel PCS
Transmitter Channel
PMA
Serializer
tx_dataout
Core
Fabric
PCI
Express
hardIP
PIPE
Interface
RX
Phase
Compensation
FIFO
Byte
Ordering
Byte
De-
serializer
8B/10
Decoder
Rate
Match
FIFO
Receiver Channel PCS
Receiver Channel
PMA
Deskew
FIFO
Word
Aligner
De-
Serializer
CDR
rx_datain
The transceiver channel datapath can be divided into the following two modes based
on the FPGA fabric-transceiver interface width (channel width) and the transceiver
channel PMA-PCS width (serialization factor):
■ Single-width mode
■ Double-width mode
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3