HC4GX15 Datasheet, PDF (339/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–75
Receiver Channel Datapath
Table 1–19 shows the word aligner configurations allowed in functional modes with
an 8-bit PMA-PCS interface.
Table 1–19. Word Aligner Configurations with an 8-Bit PMA-PCS Interface
Functional Mode
SONET/SDH OC-12
SONET/SDH OC-48
Basic single-width
Allowed Word Configurations
Manual Alignment
Manual Alignment
Manual Alignment, Bit-Slip
Allowed Word Alignment
Pattern Length
16 bits
16 bits
16 bits
Manual Alignment Mode Word Aligner with 8-Bit PMA-PCS Interface Modes
In manual alignment mode, the word aligner operation is controlled by the input
signal rx_enapatternalign. The word aligner operation is edge-sensitive to the
rx_enapatternalign signal. After de-assertion of rx_digitalreset, a rising
edge on the rx_enapatternalign signal triggers the word aligner to look for the
word alignment pattern in the received data stream. In SONET/SDH OC-12 and
OC-48 modes, the word aligner looks for 16'hF628 (A1A2) or 32'hF6F62828
(A1A1A2A2), depending on whether the input signal rx_a1a2size is driven low or
high, respectively. In Basic single-width mode, the word aligner looks for the 16-bit
word alignment pattern programmed in the ALTGX MegaWizard Plug-In Manager.
The word aligner aligns the 8-bit word boundary to the first word alignment pattern
received after the rising edge on the rx_enapatternalign signal.
Two status signals, rx_syncstatus and rx_patterndetect, with the same
latency as the datapath, are forwarded to the core fabric to indicate word aligner
status. On receiving the first word alignment pattern after the rising edge on the
rx_enapatternalign signal, both the rx_syncstatus and rx_patterndetect
signals are driven high for one parallel clock cycle synchronous to the MSByte of the
word alignment pattern. Any word alignment pattern received thereafter in the same
word boundary causes only the rx_patterndetect signal to go high for one clock
cycle.
1
For the word aligner to re-synchronize to a new word boundary, you must de-assert
rx_enapatternalign and re-assert it again to create a rising edge. After a rising
edge on the rx_enapatternalign signal, if the word alignment pattern is found in
a different word boundary, the word aligner re-synchronizes to the new word
boundary and asserts the rx_syncstatus and rx_patterndetect signals for one
parallel clock cycle.
Figure 1–60 shows word aligner behavior in SONET/SDH OC-12 functional mode.
The LSByte (8'hF6) and the MSByte (8'h28) of the 16-bit word alignment pattern are
received in parallel clock cycles n and n + 1, respectively. The rx_syncstatus and
rx_patterndetect signals are both driven high for one parallel clock cycle
synchronous to the MSByte (8'h28) of the word alignment pattern. After initial word
alignment, the 16-bit word alignment pattern is again received across the word
boundary in clock cycles m, m + 1, and m + 2. The word aligner does not re-align to
the new word boundary because of the lack of a preceding rising edge on the
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3