HC4GX15 Datasheet, PDF (56/668 Pages) Altera Corporation – HardCopy IV Device Handbook

6–6
Chapter 6: HardCopy IV Device I/O Features
HardCopy IV I/O
Figure 6–1. HardCopy IV I/O Banks (Note 1), (2), (3), (4), (5), (6), (7), (8), (9), (10)
PLL_L1 Bank 8A
Bank 8B
Bank 8C PLL_T1 PLL_T2 Bank 7C
Bank 7B
Bank 7A PLL_R1
I/O banks 8A, 8B & 8C support all
single-ended and differential input
and output operation
I/O banks 7A, 7B & 7C support all
single-ended and differential input
and output operation
PLL_L2
PLL_L3
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I and differential HSTL-12
Class I standards for input and output operation.
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15 Class II,
differential HSTL-12 Class II standards are only supported
for input operations
PLL_R2
PLL_R3
I/O banks 3A, 3B & 3C support all
single-ended and differential input
and output operation
I/O banks 4A, 4B & 4C support all
single-ended and differential input
and output operation
PLL_L4 Bank 3A
Bank 3B
Bank 3C _{PLL_B1 PLL_B2} Bank 4C
Bank 4B
Bank 4A PLL_R4
Notes to Figure 6–1:
(1) There are 12 I/O banks for the 484-pin package, 16 I/O banks for the 780-pin package, and 20 I/O banks for 1152- and 1517-pin packages.
(2) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(3) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(4) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(5) Column I/O supports PCI/PCI-X with an on-chip clamping diode. Row I/O supports PCI/PCI-X with an external clamping diode.
(6) Differential clock inputs on column I/O use V_CCCLKIN. All outputs use the corresponding bank V_CCIO.
(7) Row I/O supports the dedicated LVDS output buffer.
(8) Column I/O banks support LVPECL-only standards for input clock operation.
(9) Single-ended inputs and outputs are not allowed when true differential I/O (DPA and non-DPA) exist in an I/O bank.
(10) Figure 6–1 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation