HC4GX15 Datasheet, PDF (603/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Dynamic Reconfiguration Duration and Core Fabric Resource Utilization
2–145
For writing values to the following PMA controls, the busy signal is asserted for 520
reconfig_clk clock cycles per channel for each of these controls:
■ tx_preemp_0t (pre-emphasis control pre-tap)
■ tx_preemp_2t (pre-emphasis control second post-tap)
Read Transaction Duration
For reading the existing values of the following PMA controls, the busy signal is
asserted for 130 reconfig_clk clock cycles per channel for each of these controls.
The data_valid signal is then asserted once the busy signal goes low.
■ tx_preemp_1t_out (pre-emphasis control first post-tap)
■ tx_vodctrl_out (voltage output differential)
■ rx_eqctrl_out (equalizer control)
■ rx_eqdcgain_out (equalizer DC gain)
For reading the existing values of the following PMA controls, the busy signal is
asserted for 260 reconfig_clk clock cycles per channel for each of these controls.
The data_valid signal is then asserted once the busy signal goes low.
■ tx_preemp_0t_out (pre-emphasis control pre-tap)
■ tx_preemp_2t_out (pre-emphasis control second post-tap)
Offset Cancellation Duration
When the device powers up, the busy signal remains low for the first
reconfig_clk clock cycle. After the device powers up, it takes 70 reconfig_clk
clock cycles for the dynamic reconfiguration controller to identify the receiver
channels.
When the dynamic reconfiguration controller identifies the receiver channels and
verifies the logical channel address to physical channel mapping, it takes another 7872
reconfig_clk clock cycles per receiver channel to perform the offset cancellation
process. In other words, the busy signal goes low after 7924 reconfig_clk clock
cycles per receiver channel (50 + 2 + 7872).
1 If the design does not require PMA controls reconfiguration, each ALTGX instance in
the design can have its own dynamic reconfiguration controller (ALTGX_RECONFIG
instance). This minimizes offset cancellation duration.
Dynamic Reconfiguration Duration for Channel and TX PLL Select/Reconfig Modes
Table 2–42 shows the number of reconfig_clk clock cycles it takes for the dynamic
reconfiguration controller to reconfigure various parts of the transceiver channel and
CMU PLL.
Table 2–42. Dynamic Reconfiguration Duration for Transceiver Channel and CMU PLL
Reconfiguration (Part 1 of 2)
Transceiver Portion Under Reconfiguration
Transmitter channel reconfiguration
Receiver channel reconfiguration
Number of reconfig_clk Clock Cycles
1690 clock cycles
5181 clock cycles
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3