HC4GX15 Datasheet, PDF (117/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Differential Receiver
Figure 8–4. HardCopy IV Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
Internal
Logic
8–7
Txclkout+
Txclkout–
PLL_Lx /
PLL_Rx
diffioclk
load_en
You can bypass the HardCopy IV serializer to support DDR (×2) and SDR (×1)
operations to achieve a serialization factor of 2 and 1, respectively. The I/O element
(IOE) contains two data output registers that can each operate in either DDR or SDR
mode. The clock source for the registers in the IOE can come from any routing
resource, from the left or right PLL (PLL_Lx/PLL_Rx), or from the top or bottom
(PLL_Tx/PLL_Bx) PLL. Figure 8–5 shows the serializer bypass path.
Figure 8–5. HardCopy IV Serializer Bypass
Internal Logic
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
Serializer
Txclkout+
Txclkout–
Not used (connection exists)
Differential Receiver
HardCopy IV devices have dedicated circuitry for receiving high-speed differential
signals. Figure 8–6 shows a HardCopy IV receiver block diagram. The receiver has a
differential buffer, a shared PLL_Lx/PLL_Rx, DPA, synchronization FIFO buffer,
data realignment block, and a deserializer. The differential buffer can receive LVDS,
mini-LVDS, and RSDS signal levels, which are statically set in the Quartus II software
Assignment Editor. The PLL receives the external source clock input that is
transmitted with the data and generates different phases of the same clock. The DPA
block chooses one of the clocks from the left or right PLL and aligns the incoming data
on each channel.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1