HC4GX15 Datasheet, PDF (103/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–37
HardCopy IV External Memory Interface Features
Because the data and read strobe signals are still point-to-point, special consideration
must be taken to ensure that the timing relationship between the CK/CK# and DQS
signals (tDQSS) during a write is met at every device on the modules. Furthermore,
read data returning to the HardCopy IV ASIC from the memory is also staggered in a
similar way. HardCopy IV ASICs have leveling circuitry to compensate for the
different CK/CK# arrival time at each device in the memory module.
There is one group of leveling circuitry per I/O bank, with the same I/O number (for
example, there is one leveling circuitry shared between I/O bank 1A and 1C) located
in the middle of the I/O bank. These delay chains are PVT-compensated by the same
DQS delay settings as the DLL and DQS delay chains. The generated clock phases are
distributed to every DQS logic block that is available in the I/O bank. The delay chain
taps, then feeds a multiplexer controlled by the ALTMEMPHY megafunction to select
which clock phases are to be used for that ×4 or ×8 DQS group. Each group can use a
different tap output from the read-leveling and write-leveling delay chains to
compensate for the different CK/CK# delay going into each device on the module.
Figure 7–24 and Figure 7–25 show the HardCopy IV read-and-write leveling circuitry.
Figure 7–24. HardCopy IV Write-Leveling Delay Chains (Note 1)
Write clk
(-90⁰)
Write-Leveled DQS Clock
Write-Leveled DQ Clock
Note to Figure 7–24:
(1) There is only one leveling delay chain per I/O bank with the same I/O number (for example, I/O banks 1A and 1C). You can only have one memory
controller in these I/O banks when the leveling delay chains are used.
Figure 7–25. HardCopy IV Read-Leveling Delay Chains and Multiplexers (Note 1)
DQS
Resynchronization
clock
I/O Clock
Divider
Half-Rate Resynchronization Clock
Half-Rate Source
Synchronous Clock
Read-Leveled Resynchronization Clock
Note to Figure 7–25:
(1) There is only one leveling delay chain per I/O bank with the same I/O number (for example, I/O banks 1A and 1C). You can only have one memory
controller in these I/O banks when the leveling delay chains are used.
The –90° write clock of the ALTMEMPHY megafunction feeds the write-leveling
circuitry to produce the clock to generate the DQS and DQ signals. During
initialization, the ALTMEMPHY megafunction picks the correct write-leveled clock
for the DQS and DQ clocks for each DQS/DQ group after sweeping all the available
clocks in the write calibration process. The DQ clock output is –90° phase-shifted
compared to the DQS clock output.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1