HC4GX15 Datasheet, PDF (443/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–179
Figure 1–148 shows transceiver clocking in (OIF) CEI PHY interface mode with and
without the improved transmitter jitter option enabled.
Figure 1–148. Transceiver Clocking in (OIF) CEI PHY Interface Mode
Transceiver Block Clocking with the
Use central clock divider to improve
transmitter jitter option enabled
Channel 3
CMU PLL
CMU0 Clock
Divider Block
Channel 2
Channel 1
Channel 0
Transceiver Block Clocking with the
Use central clock divider to improve
transmitter jitter option disabled
CMU PLL
Ch 3
Local Clock Divider Block
Ch 2
Local Clock Divider Block
Ch 1
Local Clock Divider Block
Ch 0
Local Clock Divider Block
Channel 3
Channel 2
Channel 1
Channel 0
Transceiver Placement Limitations with the Use Central Clock Divider to Improve Transmitter
Jitter Option Enabled
If one or more channels in a transceiver block are configured to (OIF) CEI PHY
interface mode with the improved jitter clocking option enabled, the remaining
channels in that transceiver block must either be configured in (OIF) CEI PHY
interface mode with this option enabled or must be unused. All used channels within
a transceiver block configured in (OIF) CEI PHY interface mode with the improved
jitter clocking option enabled must also run at the same data rate.
Figure 1–149 and Figure 1–150 show two examples each of legal and illegal
transceiver placements with respect to the improved jitter clocking option in (OIF)
CEI PHY interface mode.
Figure 1–149. Examples of Legal Transceiver Placement in (OIF) CEI PHY Interface Mode
Ch 3
(OIF) CEI PHY Interface Mode with the
low-jitter option enabled
(Data Rate = 5 Gbps)
Ch 2
(OIF) CEI PHY Interface Mode with the
low-jitter option enabled
(Data Rate = 5 Gbps)
Ch 3 ^{(OIF) CEI PHY Interface Mode with the}
low-jitter option disabled
Ch 2 ^{(OIF) CEI PHY Interface Mode with the}
low-jitter option disabled
Ch 1
Unused Channel
Ch 1
Serial RapidIO
Ch 0
Unused Channel
Ch 0
Serial RapidIO
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3