HC4GX15 Datasheet, PDF (530/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–72
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Input Reference Clock Requirements for Reusing .mifs
The .mif contains information about the input clock multiplexer settings and the
functional blocks that you selected during the ALTGX MegaWizard Plug-In Manager
instantiation. When you enable the Quartus II settings described in the section, the
Quartus II software generates a .mif for each channel. You can use this .mif to
dynamically reconfigure any of the other transceiver channels in the device if you
satisfy the following two requirements for the input reference clocks:
■ The order of the clock inputs must be consistent. For example, assume that a .mif
is generated for a transceiver channel in transceiver block 0 and the input clock
source is connected to the pll_inclk_rx_cruclk [0] port. When the
generated .mif is used for a channel in other transceiver blocks (for example,
transceiver block 1), the same clock source needs to be connected to the
pll_inclk_rx_cruclk [0] port. Figure 2–35 and Figure 2–36 show the
incorrect and correct order of input reference clocks, respectively.
■ In Figure 2–35, the clocking is incorrect when reusing the .mif because the input
reference clock is not connected to the corresponding pll_inclk_rx_cruclk
[] ports in the two instances.
Figure 2–35 shows the incorrect input reference clock connections when reusing a
.mif.
Figure 2–35. Incorrect Input Reference Clock Connections When Reusing a .mif
HardCopy IV GX Device
156.25 MHz
pll_inclk_rx_cruclk[0]
Transceiver Block 0
pll_inclk_rx_cruclk[1]
ALTGX
Instance 1
125 MHz
pll_inclk_rx_cruclk[0]
Transceiver Block 1
pll_inclk_rx_cruclk[1]
ALTGX
Instance 2
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation