HC4GX15 Datasheet, PDF (431/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–167
Figure 1–135 shows the synchronization state machine implemented in GIGE mode.
Figure 1–135. Synchronization State Machine in GIGE Mode (Note 1)
power_on=TRUE+mr_main_rest=TRUE +
(signal_detectCHANGE=TRUE +
mr_loopback=FALSE +PUDI)
2
3
Note to Figure 1–135:
(1) This figure is from IEEE P802.3ae.
[PUDI * signal_detect=FAIL +
mr_loopback=FALSE] +
PUDI(![/COMMA/])
PUDI(![/|DV|/]
LOSS_OF_SYNC
sync_status ⇐ FAIL
rx_even ⇐ ! rx_even
SUDI
(signal_detect=OK+mr_loopback=TRUE)* *
PUDI([/COMMA/]
COMMA_DETECT_1
rx_even ⇐ TRUE
SUDI
PUDI([/|DV|/]
cgbad
PUDI(![/|DV|/]
ACQUIRE_SYNC_1
rx_even ⇐ ! rx_even
SUDI
PUDI(![/COMMA/]
*∉[/INVALID/]
rx_even=FALSE+PUDI([/COMMA/]
COMMA_DETECT_2
rx_even ⇐ TRUE
SUDI
PUDI([/|DV|/]
cgbad
ACQUIRE_SYNC_2
rx_even ⇐ ! rx_even
SUDI
PUDI(![/COMMA/]
*∉[/INVALID/]
rx_even=FALSE+PUDI([/COMMA/]
PUDI(![/|DV|/]
SYNC_ACQUIRED_2
rx_even ⇐ ! rx_even
SUDI
good_cgs ⇐ 0
cgbad
COMMA_DETECT_3
rx_even ⇐ TRUE
SUDI
cgbad
PUDI([/|DV|/]
cggood
SYNC_ACQUIRED_1
sync_status ⇐ OK
rx_even ⇐ ! rx_even
SUDI
cggood
SYNC_ACQUIRED_2A
rx_even ⇐ ! rx_even
SUDI
good_cgs ⇐ good_cgs + 1
cggood *good_cgs = 3
cgbad
cggood *good_cgs = 3
SYNC_ACQUIRED_3
rx_even ⇐ ! rx_even
SUDI
good_cgs ⇐ 0
cgbad
SYNC_ACQUIRED_4
rx_even ⇐ ! rx_even
SUDI
good_cgs ⇐ 0
cgbad
cggood
SYNC_ACQUIRED_3A
rx_even ⇐ ! rx_even
SUDI
good_cgs ⇐ good_cgs + 1
cggood *good_cgs = 3
cgbad
cggood
2
cggood *good_cgs = 3
SYNC_ACQUIRED_4A
rx_even ⇐ ! rx_even
SUDI
good_cgs ⇐ good_cgs + 1
cggood *good_cgs = 3
cgbad
3 _{cggood *good_cgs = 3}
Rate Match FIFO
In GIGE mode, the rate match FIFO is capable of compensating for up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The GIGE protocol requires the transmitter to send idle ordered sets
/I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps adhering to
the rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired by driving the rx_syncstatus signal
high. The rate matcher deletes or inserts both symbols (/K28.5/ and /D16.2/) of the
/I2/ ordered sets, even if it requires deleting only one symbol to prevent the rate
match FIFO from overflowing or under-running. It can insert or delete as many /I2/
ordered sets as necessary to perform the rate match operation.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3