HC4GX15 Datasheet, PDF (93/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–27
HardCopy IV External Memory Interface Features
Figure 7–17. HardCopy IV GX DLL and I/O Bank Locations (Package-Bottom View)
8A
8B
8C
PLL_T1 PLL_T2
7C
DLL1
6
6
1A
7B
7A
DLL4
6
6
6A
1C
PLL_L1
PLL_L2
2C
6C
PLL_R1
PLL_R2
5C
2A
6
6
DLL2
3A
3B
3C
PLL_B1 PLL_B2
4C
5A
6
6
DLL3
4B
4A
The DLL can access the two adjacent sides from its location within the device. For
example, DLL1 on the top left of the device can access the top side (I/O banks 7A, 7B,
7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1C, 2A, and 2C).
This means that each I/O bank is accessible by two DLLs, giving more flexibility to
create multiple frequencies and multiple-types interfaces. For example, you can
design an interface spanning one side of the device or two sides adjacent to the DLL.
The DLL outputs the same DQS delay settings for both sides of the device adjacent to
the DLL.
1 Interfaces that span across two sides of the device are not recommended for
high-performance memory interface applications.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1