HC4GX15 Datasheet, PDF (333/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–69
Receiver Channel Datapath
Figure 1–55. CDR in Lock-To-Reference Mode
rx_locktorefclk
rx_locktodata
signal detect
rx_freqlocked
rx_datain
LTR/LTD
Controller
Phase ^Down
Detector Up
(PD)
rx_cruclk /1, /2, /4
/2
Phase
Frequency
Detector
(PFD)
Up
Down
Clock and Data Recover (CDR) Unit
/2
pcie_gen2switch
High-Speed
Recovered Clock
Low-Speed
Recovered Clock
Charge Pump
+
Loop Filter
V_CO
/L
rx_pll_locked
Active Blocks
/M
Inactive Blocks
You can drive the receiver input reference clock with the following clock sources:
■ Dedicated REFCLK pins (refclk0 and refclk1) of the associated transceiver
block
■ Inter-transceiver block (ITB) clock lines from other transceiver blocks on the same
side of the device (up to six ITB clock lines, two from each transceiver block)
■ Global PLD clock driven by a dedicated clock input pin
■ Clock output from the left and right PLLs in the core fabric
Table 1–17 shows CDR specifications in LTR mode.
Table 1–17. CDR Specifications in Lock-To-Reference Mode
Parameter
Input Reference Clock Frequency
PFD Input Frequency
/M Divider
/L Divider
Value
50 MHz to 637.5 MHz
50 MHz to 325 MHz
4, 5, 8, 10, 16, 20, 25
1, 2, 4, 8
For input reference clock frequencies greater than 325 MHz, the Quartus II software
automatically selects the appropriate /1, /2, /4 pre-divider to meet the PFD input
frequency limitation of 325 MHz.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3