HC4GX15 Datasheet, PDF (185/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Design Flow Using the Quartus II Software
1–17
Incremental Compilation
Top-Down Incremental Compilation
Top-down incremental compilation is supported for the base revision for designs
targeting HardCopy ASICs in both the FPGA first flow and HardCopy first flow. In
the Quartus II design software, you must select the base and companion revisions
before design partitions of the base revision are created.
After the design partitions are created in the Quartus II design software, the base
revision is compiled and the design partition assignments are mapped to the
companion device. In the HardCopy development flow, you make changes only in
the base revision's design and design partition assignments with the Quartus II
design software. Therefore, you can perform top-down incremental compilation only
in the base revision, but cannot perform incremental compilation to the companion
revision. Figure 1–8 shows the design “Top” with two design partitions.
Figure 1–8. Quartus II Project with Design Partitions
Top
Partition “inst3”
Partition “inst2”
After the design partitions are created and compiled in the base family revision, you
can modify the specific design partitions for additional area and performance
improvement. Figure 1–9 shows that when the logic is modified in partition “inst3”
the Quartus II software is ready to re-compile the individual hierarchical design
partition separately, based on the preservation level in the Design Partition Window.
Therefore, the optimization result of design partitions “top” and “inst2” are preserved
while the partition “inst3” is re-compiled in the Quartus II design software.
Figure 1–9. Design Partition Modified
Top
Partition “inst3”
Partition “inst2”
(No Change)
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 2