HC4GX15 Datasheet, PDF (218/668 Pages) Altera Corporation – HardCopy IV Device Handbook

3–16
Chapter 3: Mapping Stratix IV Device Resources to HardCopy IV Devices
Designing with HardCopy IV I/Os
Table 3–10. I/O Standards and Voltage Levels for HardCopy IV Devices (Part 2 of 2) (Note 1)
I/O Standard
Standard
Support
V_CCIO (V)
Input Operation
Output Operation
Column
I/O Banks
Row I/O
Banks
Column Row I/O
I/O Banks Banks
V_CCPD (V)
(Pre-Driver
Voltage)
V_REF (V)
(Input Ref
Voltage)
V_TT (V) (Board
Termination
Voltage)
Differential HSTL-18
Class I
JESD8-6
(3)
(3)
1.8
1.8
2.5
—
0.90
Differential HSTL-18
Class II
JESD8-6
(3)
(3)
1.8
1.8
2.5
—
0.90
Differential HSTL-15
Class I
JESD8-6
(3)
(3)
1.5
1.5
2.5
—
0.75
Differential HSTL-15
Class II
JESD8-6
(3)
(3)
1.5
—
2.5
—
0.75
Differential HSTL-12
Class I
JESD8-16A
(3)
(3)
1.2
1.2
2.5
—
0.60
Differential HSTL-12
Class II
JESD8-16A
(3)
(3)
1.2
—
2.5
—
0.60
LVDS (4), (5)
ANSI/TIA/
EIA-644
(3)
(3)
2.5
2.5
2.5
—
—
RSDS (6), (7)
—
(3)
(3)
2.5
2.5
2.5
—
—
mini-LVDS (6), (7)
—
(3)
(3)
2.5
2.5
2.5
—
—
LVPECL
—
(4)
2.5
—
—
2.5
—
—
Notes to Table 3–10:
(1) V_CCPD is either 2.5 or 3.0 V. For V_CCIO = 3.0 V, V_CCPD = 3.0 V. For V_CCIO = 2.5 V or less, V_CCPD = 2.5 V.
(2) The 3.3-V LVTTL/LVCMOS standard is supported using VCCIO at 3.0 V.
(3) Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by V_CCPD. Row I/O banks support both true differential
input buffers and true differential output buffers. Column I/O banks support true differential input buffers, but not true differential output buffers.
I/O pins are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers
without on-chip R_D support.
(4) Column I/O banks support LVPECL I/O standards for input clock operation. Clock inputs on column I/O are powered by V_CCCLKIN when configured
as differential clock input. They are powered by V_CCIO when configured as single-ended clock input. Differential clock inputs in row I/O are
powered by V_CCPD.
(5) Column and row I/O banks support LVDS outputs using two single-ended output buffers, an external one-resistor (LVDS_E_1R), and a
three-resistor (LVDS_E_3R) network.
(6) Row I/O banks support RSDS and mini-LVDS I/O standards using a dedicated LVDS output buffer without a resistor network.
(7) Column and row I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with one-resistor (RSDS_E_1R
and mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks.
External Memory Interface I/Os in Stratix IV and HardCopy IV Devices
As with the Stratix IV I/O structure, the redesign of the HardCopy IV I/O structure
provides flexible and high-performance support for existing and emerging external
memory standards including DDR3, DDR2, DDR SDRAM, QDRII+, QDRII SRAM,
and RLDRAM II.
HardCopy IV devices offer the same external memory interface features found in
Stratix IV devices. These features include delay-locked loops (DLLs), phase-locked
loops (PLLs), dynamic on-chip termination (OCT), trace mismatch compensation,
read and write leveling, deskew circuitry, half data rate (HDR) blocks, 4- to 36-bit DQ
group widths, and DDR external memory support on all sides of the HardCopy IV
device.
HardCopy IV Device Handbook, Volume 2
© January 2010 Altera Corporation