HC4GX15 Datasheet, PDF (291/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–27
CMU Channels
When you set the rateswitch port to 0, the PCI Express (PIPE) rateswitch controller
(in the CCU) signals the PCIE rateswitch circuit to select the divide by /2 to provide a
high-speed serial clock for the Gen1 (2.5 Gbps) data rate. When the rateswitch port
is set to 1, the /N divider output is forwarded, providing a high-speed serial clock for
the Gen2 (5 Gbps) data rate to the transmitter channels.
1 The PCIE rateswitch circuit performs the rateswitch operation only for the transmitter
channels. For the receiver channels, the rateswitch circuit within the receiver CDR
performs the rateswitch operation.
The PCIE rateswitch circuit is controlled by the PIPE rateswitch controller in the CCU.
The PIPE rateswitch controller asserts the pipephydonestatus signal for one clock
cycle after the rateswitch operation is completed for both the transmit and receive
channels. Figure 1–11 shows the timing diagram for the rateswitch operation.
For more information about PCI Express (PIPE) functional mode rateswitch, refer to
“PCI Express (PIPE) Gen2 (5 Gbps) Support” on page 1–137.
Figure 1–11. Rateswitch in PCI Express (PIPE) Mode (Note 1)
250 MHz (Gen 1)
Low-Speed Parallel Clock
500 MHz (Gen 2)
250 MHz (Gen 1)
rateswitch
pipephydonestatus
T1
T1
Note to Figure 1–11:
(1) Time T1 is pending characterization.
1 When you create a PIPE Gen2 configuration, configure the CMU PLL to 5 Gbps. This
helps to generate the 2.5 Gbps and 5 Gbps high-speed serial clock using the rateswitch
circuit.
Low-Speed Parallel Clock Generation
The /S divider receives the clock output from the /N divider or PCIE rateswitch
circuit (only in PIPE mode) and generates the low-speed parallel clock for the PCS
block of all transmitter channels and coreclkout for the core fabric. If the byte
serializer block is enabled in bonded channel modes, the /S divider output is divided
by the /2 divider and sent out as coreclkout to the core fabric. The Quartus II
software automatically selects the /S values based on the deserialization width setting
(single-width mode or double-width mode) that you select in the ALTGX
MegaWizard Plug-In Manager. For more information about single-width or double-
width mode, refer to “Transceiver Channel Architecture” on page 1–34.
1 The Quartus II software automatically selects all the divider settings based on the
input clock frequency, data rate, deserialization width, and channel width settings.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3