HC4GX15 Datasheet, PDF (398/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–134
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
The PCI Express (PIPE) interface in HardCopy IV GX transceivers provides an input
port, powerdn[1:0], for each transceiver channel configured in PIPE mode.
Table 1–33 shows mapping between the logic levels driven on the powerdn[1:0]
port and the resulting power state that the PIPE interface block puts the transceiver
channel into.
Table 1–33. Power State Functions and Descriptions
Power State
P0
P0s
P1
P2
powerdn
2’b00
2’b01
2’b10
2’b11
Function
Description
Transmits normal data, transmits electrical idle, or Normal operation mode
enters into loopback mode
Only transmits electrical idle
Low recovery time saving state
Transmitter buffer is powered down and can do a High recovery time power saving
receiver detect while in this state
state
Transmits electrical idle or a beacon to wake up the Lowest power saving state
downstream receiver
1 When transitioning from the P0 power state to lower power states (P0s, P1, and P2),
the PIPE specification requires the physical layer device to implement power saving
measures. HardCopy IV GX transceivers do not implement these power saving
measures except putting the transmitter buffer in electrical idle in the lower power
states.
The PIPE interface block indicates successful power state transition by asserting the
pipephydonestatus signal for one parallel clock cycle as specified in the PIPE
specification. The PHY-MAC layer must not request any further power state
transition until the pipephydonestatus signal has indicated the completion of the
current power state transition request.
Figure 1–112 shows an example waveform for a transition from the P0 to P2 power
state.
Figure 1–112. Power State Transition from P0 to P2
Parallel
Clock
powerdn[1:0]
2'b00 (P0)
2'b11 (P2)
pipephydonestatus
The PIPE specification allows the PIPE interface to perform protocol functions; for
example, receiver detect, loopback, and beacon transmission, in specified power
states only. This requires the PHY-MAC layer to drive the tx_detectrxloopback
and tx_forceelecidle signals appropriately in each power state to perform these
functions. Table 1–34 summarizes the logic levels that the PHY-MAC layer must drive
on the tx_detectrxloopback and tx_forceelecidle signals in each power
state.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation