HC4GX15 Datasheet, PDF (412/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
Figure 1–118. Low-Speed Parallel Clock Switching in PCI Express (PIPE) ×8 Mode (Note 1)
Low-Speed Parallel Clock
250 MHz (Gen1)
500 MHz (Gen2)
250 MHz (Gen1)
rateswitch
pipephydonestatus[7]
pipephydonestatus[0]
T1
T1
Note to Figure 1–118:
(1) Time T1 from a transition on the rateswitch signal to the assertion of pipephydonestatus is pending characterization.
As a result of the signaling rateswitch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps),
the core fabric-transceiver interface clock switches between 125 MHz and 250 MHz.
The core fabric-transceiver interface clock clocks the read side and write side of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO of
all eight bonded channels, respectively. It is also routed to the core fabric on a global
or regional clock resource and looped back to clock the write port and read port of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO,
respectively. Due to the routing delay between the write and read clock of the
transmitter and receiver phase compensation FIFOs, the write pointers and read
pointers might collide during a rateswitch between 125 MHz and 250 MHz. To avoid
collision of the phase compensation FIFO pointers, the PIPE rateswitch controller
automatically disables and resets the phase compensation FIFO pointers of all eight
bonded channels during clock switch. When the PIPE clock switch circuitry in the
local clock divider indicates successful clock switch completion, the PIPE rateswitch
controller releases the phase compensation FIFO pointer resets.
PCI Express (PIPE) Cold Reset Requirements
The PIPE Base Specification 2.0 defines the following three types of conventional
resets to the PIPE system components:
■ Cold reset—fundamental reset after power up
■ Warm reset—fundamental reset without removal and re-application of power
■ Hot reset—In-band conventional reset initiated by the higher layer by setting the
Hot Reset bit in the TS1 or TS2 training sequences
Fundamental reset is provided by the system to the component or adapter card using
the auxiliary signal PERST#. The PIPE Base Specification 2.0 specifies that PERST#
must be kept asserted for a minimum of 100 ms (TPVPERL) after the system power
becomes stable in a cold reset situation. Additionally, all system components must
enter the LTSSM Detect state within 20 ms and the link must become active within
100 ms after de-assertion of the PERST# signal. This implies that each PIPE system
component must become active within 200 ms after the power becomes stable.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation