HC4GX15 Datasheet, PDF (331/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–67
Receiver Channel Datapath
The HardCopy IV GX receiver buffer also supports programmable DC gain circuitry.
Unlike equalization circuitry, DC gain circuitry provides equal boost to the incoming
signal across the frequency spectrum. The receiver buffer supports DC gain settings of
0, 3, 6, 9, and 12 dB. You can select the appropriate DC gain setting in the ALTGX
MegaWizard Plug-In Manager.
Signal Threshold Detection Circuitry
In PCI Express (PIPE) mode, you can enable the optional signal threshold detection
circuitry by not selecting the Force signal detection option in the ALTGX
MegaWizard Plug-In Manager. If enabled, this option senses whether the signal level
present at the receiver input buffer is above the signal detect threshold voltage that
you specified in the What is the signal detect and signal loss threshold? option in the
ALTGX MegaWizard Plug-In Manager.
1 The appropriate signal detect threshold level that complies with the PIPE compliance
parameter VRX-IDLE-DETDIFFp-p is pending characterization.
Signal threshold detection circuitry has a hysteresis response that filters out any
high-frequency ringing caused by inter-symbol interference or high-frequency losses
in the transmission medium. If the signal threshold detection circuitry senses the
signal level present at the receiver input buffer to be higher than the signal detect
threshold, it asserts the rx_signaldetect signal high. Otherwise, the signal
threshold detection circuitry de-asserts the rx_signaldetect signal low. If you
select the Force signal detection option in the ALTGX MegaWizard Plug-In Manager,
rx_signaldetect is always asserted high, irrespective of the signal level on the
receiver input buffer.
The rx_signaldetect signal is also used by the lock-to-reference/lock-to-data
(LTR/LTD) controller in the receiver CDR to switch between the LTR and LTD lock
modes. When the signal threshold detection circuitry de-asserts the
rx_signaldetect signal, the LTR/LTD controller switches the receiver CDR from
LTD to LTR lock mode. For more information, refer to “LTR/LTD Controller” on
page 1–71.
Clock and Data Recovery Unit
Each HardCopy IV GX receiver channel has an independent CDR unit to recover the
clock from the incoming serial data stream. The high-speed and low-speed recovered
clocks are used to clock the receiver PMA and PCS blocks. Figure 1–54 shows the CDR
block diagram.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3