HC4GX15 Datasheet, PDF (124/668 Pages) Altera Corporation – HardCopy IV Device Handbook

8–14
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Clocking
Clocking
The left and right PLLs feed into the differential transmitter and receiver channels
through the LVDS and DPA clock networks. Figure 8–14 and Figure 8–15 show the
corner and center PLL clock in HardCopy IV devices. Each left or right I/O bank
consists of one LVDS clock network, for a total of four clock trees on the device. The
center left and right PLLs can drive the LVDS clock network, therefore, clocking the
transmitter and receiver channels above and below them. The corner left and right
PLLs can drive the adjacent row-I/O banks only. For example, corner PLL_L1 can
drive the LVDS clock network only in I/O bank 1A and bank 1C. Therefore, with
corner PLLs, each LVDS clock network can be driven by three PLLs: two center PLLs
and one corner PLL. For HardCopy IV devices without a corner PLL, each clock tree
can be driven by two center PLLs. Each clock network supports two full-duplex
transceiver channels. However, Altera recommends you share the diffioclk and
load_en signals between transmitting and receiving channels in the same I/O bank
whenever possible. For more information about PLL clocking restrictions, refer to
“Differential Pin Placement Guidelines” on page 8–16.
Figure 8–14. LVDS/DPA Clocks in HardCopy IV and Stratix IV Devices with Center PLLs
LVDS
4 Clock
DPA
Clock
Network Network
4
2 ^Center
PLL_L2
2
Center
PLL_L3
4
LVDS
DPA
4 _Clock
Clock
Network Network
Quadrant
Quadrant
Quadrant
Quadrant
DPA
LVDS
Clock Clock 4
Network Network
4
Center
PLL_R2
2
2
Center
PLL_R3
4
DPA
LVDS
Clock
Clock 4
Network Network
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation