HC4GX15 Datasheet, PDF (189/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Design Flow Using the Quartus II Software
1–21
Timing Closure and Verification
Figure 1–13 shows the HardCopy Design Readiness Check in the Quartus II software.
Figure 1–13. HardCopy Design Readiness Check in the Quartus II Software
f For more information about the HardCopy Design Readiness Check, refer to the
Quartus II Support for HardCopy Series Devices chapter in volume 1 of the Quartus II
Handbook.
Timing Closure and Verification
After compiling the project for the Stratix IV and HardCopy IV designs, check the
device used and verify that the design meets your timing requirements. Analyze the
messages generated by the Quartus II software during compilation to check for any
potential problems. Also verify the design functionality between the Stratix IV and
HardCopy IV devices with the HardCopy Companion Revision Comparison option
in the Quartus II software.
Timing Closure with the TimeQuest Timing Analyzer
The TimeQuest Timing Analyzer is the timing analysis tool for all HardCopy IV
devices during the front-end design process; it is the default timing analyzer for
Stratix IV and HardCopy IV devices in the Quartus II software.
After you specify the initial timing constraints that describe the clock characteristics,
timing exceptions, and signal transition arrival and required time in the .sdc, the
TimeQuest analyzer analyzes the timing paths in the design, calculates the
propagation delay along each path, checks for timing constraint violations, and
reports timing results.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 2