HC4GX15 Datasheet, PDF (406/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–142
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
The PCI Express (PIPE) clock switch circuitry in the local clock divider block performs
the clock switch between 250 MHz and 500 MHz on the low-speed parallel clock
when switching between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rates. It
indicates successful completion of clock switch on the pcie_gen2switchdone
signal to the PIPE rateswitch controller. The PIPE rateswitch controller forwards the
clock switch completion status to the PIPE interface block. The PIPE interface block
communicates the clock switch completion status to the PHY-MAC layer by asserting
the pipephydonestatus signal for one parallel clock cycle.
Figure 1–114 shows low-speed parallel clock switch between Gen1 (250 MHz) and
Gen2 (500 MHz) in response to the change in the logic level on the rateswitch
signal. The rateswitch completion is shown marked with a one clock cycle assertion of
the pipephydonestatus signal.
1 Time T1 from a transition on the rateswitch signal to the assertion of
pipephydonestatus is pending characterization.
Figure 1–114. Low-Speed Parallel Clock Switching in PCI Express (PIPE) ×1 Mode
Low-Speed Parallel Clock
250 MHz (Gen1)
500 MHz (Gen2)
250 MHz (Gen1)
rateswitch
pipephydonestatus
T1
T1
As a result of the signaling rateswitch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps),
the core fabric-transceiver interface clock switches between 125 MHz and 250 MHz.
The core fabric-transceiver interface clock clocks the read side and write side of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO,
respectively. It is also routed to the core fabric on a global or regional clock resource
and looped back to clock the write port and read port of the transmitter phase
compensation FIFO and the receiver phase compensation FIFO, respectively. Due to
the routing delay between the write and read clock of the transmitter and receiver
phase compensation FIFOs, the write pointers and read pointers might collide during
a rateswitch between 125 MHz and 250 MHz. To avoid collision of the phase
compensation FIFO pointers, the PIPE rateswitch controller automatically disables
and resets the pointers during clock switch. When the PIPE clock switch circuitry in
the local clock divider indicates successful clock switch completion, the PIPE
rateswitch controller releases the phase compensation FIFO pointer resets.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation