HC4GX15 Datasheet, PDF (541/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–83
Description of Transceiver Channel Reconfiguration Modes
Figure 2–41. Option 2 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
ASIC Core
Transciever Block
tx_clkout[0]
TX0 (3 Gbps)
RX0
tx_clkout[1]
tx_clkout[2]
TX1 (3 Gbps)
RX1
TX2 (3 Gbps)
RX2
CMU1 PLL
CMU0 PLL
tx_clkout[3]
TX3 (3 Gbps)
RX3
High-speed serial clock generated by the CMU0 PLL
Table 2–27. Receiver Core Clocking (Part 1 of 2)
Receiver core clocking refers to the clock that is used to read the parallel data from the Receiver Phase Compensation FIFO
into the core fabric. You can use one of the following clocks to read from the Receive Phase Compensation FIFO:
■ rx_coreclk—You can use a clock of the same frequency as rx_clkout from the core fabric to provide the read
clock to the Receive Phase Compensation FIFO. If you use rx_coreclk, it overrides the rx_clkout options in the
ALTGX MegaWizard Plug-In Manager.
■ rx_clkout—The Quartus II software automatically routes rx_clkout to the core fabric and back into the Receive
Phase Compensation FIFO. There are three options available within the rx_clkout option in the Reconfig 2 screen.
The following are the three rx_clkout options in the Reconfig 2 screen of the ALTGX MegaWizard Plug-In Manager (1):
Option 1: Share a Single
Option 2: Use Respective Channel
Transmitter Core Clock between Transmitter Core Clocks
Receivers
Option 3: Use Respective Channel
Receiver Core Clocks
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3