HC4GX15 Datasheet, PDF (646/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
1–16
Switching Characteristics
Table 1–20. HardCopy IV GX Transceiver Specifications (Part 5 of 5)
Symbol
Parameter
Minimum
Typical Maximum
Unit
Digital reset pulse width
Minimum is 2
—
parallel clock
—
—
—
cycles
Notes to Table 1–20:
(1) The -2X speed grade is the fastest speed grade offered in the following HardCopy IV GX devices: HC4GX15LF780N, HC4GX25LF780N,
HC4GX25LF1152N, HC4GX25FF1152N, HC4GX35FF1152N, HC4GX35LF1517N and HC4GX35FF1517N.
(2) The minimum reconfig_clk frequency is 2.5MHz if the transceiver channel is configured in transmitter only mode. The minimum reconfig_clk
frequency is 37.5MHz if the transceiver channel is configured in receiver only or receiver and transmitter mode. For more details, refer to
HardCopy IV Dynamic Reconfiguration chapter in volume 3 of the HardCopy IV Device Handbook.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The 1.1-V RX VICM setting must be used if the input serial data standard is LVDS and the link is DC coupled.
(5) The rate matcher supports only up to +/- 300ppm.
(6) Time taken to rx_pll_locked goes high from rx_analogreset deassertion. Refer to Figure 1–2.
(7) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual
mode. Refer to Figure 1–2.
(8) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–2.
(9) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–3.
(10) A GPLL may be required to meet PMA-HardCopy fabric interface timing above certain data rates and this requirement is same as PMA-FPGA
fabric interface. Refer to section “Left/Right PLL Requirements in Basic (PMA Direct) Mode” in the Stratix IV Transceiver Clocking chapter in
volume 2 of the Stratix IV Device Handbook.
(11) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(12) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the
link. You can bond all channels on one side of the device by configuring them in Basic (PMA-Direct) xN mode. Refer to the Basic (PMA Direct)
mode clocking section in the Stratix IV Transceiver Clocking chapter for details on clocking requirements in this mode.
(13) Pending characterization.
(14) The Quartus II software automatically selects the appropriate /L divider depending upon the configured data rate.
Figure 1–2 shows the lock time parameters in manual mode. Figure 1–3 shows the
lock time parameters in automatic mode.
1 LTD = Lock-To-Data LTR = Lock-To-Reference
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 4