HC4GX15 Datasheet, PDF (564/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–106
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Channel Reconfiguration with TX PLL Select: Operation
In channel reconfiguration, only a write transaction can occur; no read transactions
are allowed.
■ Set the reconfig_mode_sel[2:0] control signal to 3’b001 to use the channel
reconfiguration feature. When you use this feature, the dynamic reconfiguration
controller requires that you provide a 16-bit word (reconfig_data[15:0]) on
every write transaction using the write_all signal. This 16-bit word is part of a
.mif that is generated by the Quartus II software when an ALTGX instance is
compiled.
■ Set the rx_tx_duplex_sel[1:0] port to enable the transmitter, receiver, or
receiver and transmitter portion for reconfiguration.
■ Set the logical_channel_address port to specify the logical channel address
of the transceiver channel.
■ Ensure the busy signal is low and assert the write_all signal for one
reconfig_clk clock cycle.
■ Figure 2–47 depicts a .mif write transaction when dynamically reconfiguring a
transceiver channel. The .mif write transaction in Channel Reconfiguration with
TX PLL Select mode remains the same, except for the value you must set at
reconfig_mode_sel[2:0] and the differences in the .mif words utilized.
■ Set reconfig_mode_sel[2:0] to 3'b001 for Channel Reconfiguration with TX
PLL Select mode.
CMU PLL Reconfiguration Mode
You can use this mode to reconfigure only the CMU PLL without affecting the
remaining blocks of the transceiver channel. When you reconfigure the CMU PLL of a
transceiver block to run at a different data rate, all the transceiver channels listening to
this CMU PLL also get reconfigured to the new data rate.
This reconfiguration mode is a .mif-based approach.
1 CMU PLL Reconfiguration mode is applicable only to regular transceiver channels
configured in non-Basic (PMA Direct) modes.
1 CMU PLL Reconfiguration mode is not applicable to bonded, Basic (PMA Direct) ×1,
Basic (PMA Direct) ×N, and CEI configurations.
1 The logical_channel_address port is not applicable in CMU PLL
Reconfiguration mode, even though it is available as an input.
TX PLL Powerdown
During CMU PLL Reconfiguration mode, the dynamic reconfiguration controller
automatically powers down the selected CMU PLL until it completes reconfiguration.
The ALTGX_RECONFIG instance does not provide any external ports to control the
CMU PLL power down. When you reconfigure the CMU PLL, the pll_locked
signal goes low. Therefore, after reconfiguring the transceiver, wait for the
pll_locked signal from the ALTGX instance before continuing normal operation.
The dynamic reconfiguration controller powers down only the selected CMU PLL.
The other CMU PLL is not affected.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation