HC4GX15 Datasheet, PDF (402/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
■ Dynamically selectable transmitter margining for differential output voltage
control
■ Dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 dB
■ Dynamically selectable full-swing and half-swing transmitter output voltage
levels
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rate
During link training, the upstream and downstream PCI Express (PIPE) ports
negotiate the speed (2.5 Gbps or 5 Gbps) at which the link operates. Because the
upstream and downstream PIPE ports do not know the speed capabilities of their link
partner, the PIPE protocol requires each port to start with a Gen1 (2.5 Gbps) signaling
rate. One of the ports capable of supporting the Gen2 (5 Gbps) signaling rate might
initiate a speed change request by entering the Recovery state of the LTSSM. In the
Recovery state, each port advertises its speed capabilities by transmitting training
sequences as specified in the PIPE Base Specification 2.0. If both ports are capable of
operating at the Gen2 (5 Gbps) signaling rate, the PHY-MAC layer instructs the
physical layer device to operate at the Gen2 (5 Gbps) signaling rate.
To support speed negotiation during link training, the PIPE specification requires a
PIPE-compliant physical layer device to provide an input signal (Rate) to the
PHY-MAC layer. When this input signal is driven low, the physical layer device must
operate at the Gen1 (2.5 Gbps) signaling rate; when driven high, this input signal
must operate at the Gen2 (5 Gbps) signaling rate. The PIPE specification allows the
PHY-MAC layer to initiate a signaling rateswitch only in power states P0 and P1 with
the transmitter buffer in Electrical Idle state. The PIPE specification allows the
physical layer device to implement the signaling rateswitch using either of the
following approaches:
■ Change the transceiver datapath clock frequency, keeping the transceiver interface
width constant
■ Change the transceiver interface width between 8 bit and 16 bit, keeping the
transceiver clock frequency constant
When configured in PIPE functional mode at Gen2 (5 Gbps) data rate, the ALTGX
MegaWizard Plug-In Manager provides the input signal rateswitch. The
rateswitch signal is functionally equivalent to the Rate signal specified in the PIPE
specification. The PHY-MAC layer can use the rateswitch signal to instruct the
HardCopy IV GX device to operate at either Gen1 (2.5 Gbps) or Gen2 (5 Gbps) data
rate, depending on the negotiated speed between the upstream and downstream
ports. A low-to-high transition on the rateswitch signal initiates a data rateswitch
from Gen1 (2.5 Gbps) to Gen2 (5 Gbps). A high-to-low transition on the rateswitch
signal initiates a data rateswitch from Gen2 (5 Gbps) to Gen1 (2.5 Gbps). The signaling
rateswitch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) is achieved by changing the
transceiver datapath clock frequency between 250 MHz and 500 MHz, while
maintaining a constant transceiver interface width of 16-bit.
The dedicated PIPE rateswitch circuitry performs the dynamic switch between the
Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rate. The PIPE rateswitch circuitry
consists of:
■ PCI Express (PIPE) rateswitch controller
■ PCI Express (PIPE) clock switch circuitry
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation