HC4GX15 Datasheet, PDF (88/668 Pages) Altera Corporation – HardCopy IV Device Handbook

7–22
Chapter 7: External Memory Interfaces in HardCopy IV Devices
Memory Interfaces Pin Support
For more information about the parity, ECC, and QVLD pins, and when these pins are
treated as DQ pins, refer to “Data and Data Clock/Strobe Pins” on page 7–6.
Address and Control/Command Pins
Address and control/command signals are typically sent at single data rate. The only
exception is in QDRII SRAM burst-of-two devices, in which case the read address
must be captured on the rising edge of the clock and the write address must be
captured on the falling edge of the clock by the memory. There is no special circuitry
required for the address and control/command pins. You can use any of the user I/O
pins in the same I/O bank as the data pins.
Memory Clock Pins
In addition to DQS (and CQn) signals to capture data, DDR3, DDR2, DDR SDRAM,
and RLDRAM II use an extra pair of clocks, called CK and CK# signals, to capture the
address and control/command signals. The CK and CK# signals must be generated to
mimic the write data-strobe using HardCopy IV DDR I/O registers (DDIOs) to ensure
that the timing relationships between the CK, CK#, and DQS signals (tDQSS in DDR3,
DDR2, and DDR SDRAM or tCKDK in RLDRAM II) are met. QDRII+ and
QDRII SRAM devices use the same clock (K/K#) to capture the data, address, and
control/command signals.
Memory clock pins in HardCopy IV devices are generated using a DDIO register
going to differential output pins, marked in the pin table with DIFFOUT, DIFFIO_TX,
and DIFFIO_RX prefixes. For more information about which pins to use for memory
clock pins, refer to Table 7–4 on page 7–8.
Figure 7–14 shows memory clock generation for HardCopy IV devices.
Figure 7–14. Memory Clock Generation Block Diagram (Note 1)
HardCopy HCells
I/O Elements
V_CC
System Clock
DQ
DQ
CK or DK or K (2)
CK# or DK# or K# (2)
Notes to Figure 7–14:
(1) For the pin location requirements for these pins, refer to Table 7–3 on page 7–7.
(2) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback. For memory
interfaces using a differential DQS input, the input feedback buffer is configured as differential input; for memory interfaces using a single-ended
DQS input, the input buffer is configured as a single-ended input. Using a single-ended input feedback buffer requires that V_REF is provided to that
I/O bank’s VREF pins.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation