HC4GX15 Datasheet, PDF (73/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–7
Memory Interfaces Pin Support
Table 7–3 lists the pin connections between a HardCopy IV device and an external
memory device.
Table 7–3. HardCopy IV Memory Interfaces Pin Utilization
Pin Description
Memory Standard
HardCopy IV Pin Utilization
Read Data
All
DQ
Write Data
All
DQ (1)
Parity, DM, BWSn,
NWSn, QVLD, ECC
All
DQ (1), (2)
DDR3 SDRAM DDR2 SDRAM (with
differential DQS signaling) (3)
RLDRAM II
Differential DQS/DQSn
DDR2 SDRAM (with single-ended DQS
Read Strobes/Clocks _{signaling) (3)}
Single-ended DQS
DDR SDRAM
QDRII+ SRAM
QDRII SRAM
Complementary DQS/CQn
QDRII+ SRAM (4)
Write Clocks
QDRII SRAM (4)
Any unused DQS and DQSn pin pairs (1)
RLDRAM II SIO
DDR3 SDRAM
Any unused DQ or DQS pins with DIFFIO_RX capability
for the mem_clk[0] and mem_clk_n[0] signals.
Any unused DQ or DQS pins with DIFFOUT capability for
the mem_clk[n:1] and mem_clk_n[n:1] signals
(where n is greater than or equal to 1).
Memory Clocks
DDR2 SDRAM (with differential DQS
signaling)
Any DIFFIO_RX pins for the mem_clk[0] and
mem_clk_n[0] signals.
Any unused DIFFOUT pins for the mem_clk[n:1] and
mem_clk_n[n:1] signals (where n is greater than or
equal to 1).
DDR2 SDRAM (with single-ended DQS
signaling)
DDR SDRAM
Any DIFFOUT pins
RLDRAM II
QDRII+ SRAM (4)
QDRII SRAM (4)
Any unused DQSn pin pairs (1)
Notes to Table 7–3:
(1) If the write data signals are unidirectional including the data mask pins, connect them to a separate DQS/DQ group other than the read DQS/DQ
group. Connect the write clock to the DQS and DQSn pin-pair associated with that DQS/DQ group. Do not use the DQS and CQn pin-pair as
write clocks.
(2) The BWSn, NWSn, and DM pins must be part of the write DQS/DQ group. Parity, QVLD, and ECC pins must be part of the read DQS/DQ group.
(3) DDR2 SDRAM supports either single-ended or differential DQS signaling.
(4) QDRII+/QDRII SRAM devices typically use the same clock signals for both write and memory clock pins (K/K# clocks) to latch data and address,
and command signals. The clocks must be part of the DQS/DQ group in this case.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1