HC4GX15 Datasheet, PDF (108/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 7: External Memory Interfaces in HardCopy IV Devices
HardCopy IV External Memory Interface Features
Output Buffer Delay
In addition to allowing for output buffer duty-cycle adjustment, the output buffer
delay chain allows you to adjust the delays between the data bits in your output bus
to introduce or compensate channel-to-channel skew. Incorporating skew to the
output bus can help minimize simultaneous switching events by enabling smaller
parts of the bus to switch simultaneously instead of the whole bus. This feature is
useful in DDR3 SDRAM interfaces where the memory system clock delay can be
much larger than the data and data clock/strobe delay. You can use this delay chain to
add delay to the data and data clock/strobe to better match the memory system clock
delay.
Slew Rate Control
HardCopy IV devices provide four levels of static output slew rate control: 0, 1, 2, and
3; Level 0 is the slowest slew rate setting and level 3 is the fastest slew rate setting. The
default setting for the HSTL and SSTL I/O standards is 3. A fast slew rate setting
allows you to achieve higher I/O performance, and a slow slew-rate setting reduces
system noise and signal overshoot. This feature is disabled if you use the OCT R_S
features.
Drive Strength
You can choose the optimal drive strength required for your interface after
performing board simulation. Higher drive strength helps provide a larger voltage
swing, which in turn provides bigger eye diagrams with greater timing margin.
However, higher drive strengths typically require more power, result in faster slew
rates, and add to simultaneous switching noise. You can use the slew rate control with
this feature to minimize simultaneous switching noise (SSN) with higher drive
strengths. This feature is also disabled if you use the OCT R_S feature, which is the
default drive strength in HardCopy IV devices. Use the OCT R_T/R_S setting for
unidirectional read-and-write data and the dynamic OCT setting for bidirectional
data signals. You must simulate the system to determine the drive strength required
for command, address, and clock signals.
PLL
You can use PLLs to generate the memory interface controller clocks, such as the
0° system clock, the –90° or 270° phase-shifted write clock, the half-rate PHY clock,
and the resynchronization clock. You can also use the PLL reconfiguration feature to
calibrate the resynchronization phase shift to balance the setup and hold margin. The
VCO and counter setting combinations may be limited for high-performance memory
interfaces.
Altera recommends enabling the PLL reconfiguration feature and the DLL phase
offset feature (DLL reconfiguration) for HardCopy IV devices. Because HardCopy IV
devices are mask programmed, they cannot be changed after the silicon is fabricated.
By implementing these two features, you can perform timing adjustments to improve
or resolve timing issues after the silicon is fabricated.
f For more information about HardCopy IV PLLs, refer to the Clock Networks and PLLs
in HardCopy IV Devices chapter.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation