HC4GX15 Datasheet, PDF (467/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–9
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration
For PMA controls reconfiguration, the dynamic reconfiguration control inputs to the
controller are translated into address and data bus. The address and data bus are then
converted into serial data and forwarded to the transceiver channel selected.
For the data rate division control logic to the TX local divider, the
rate_switch_ctrl[1:0] input to the controller is translated into address and data
bus. The address and data bus are then converted into serial data and forwarded to
the local divider in the transmitter channel.
For the CMU PLL reconfiguration, Channel and CMU PLL reconfiguration, and
Channel reconfiguration with TX PLL select modes, the dynamic reconfiguration
controller receives 16-bit words from a .mif that you generate and sends this
information to the transceiver channel selected. For more information regarding .mif
generation, refer to “.mif Generation” on page 2–69.
Dynamic Reconfiguration Controller Interface
The dynamic reconfiguration controller interface consists of certain control input and
output status signals. Figure 2–4 shows the dynamic reconfiguration interface list,
which contains all the inputs and outputs to the dynamic reconfiguration controller.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3