HC4GX15 Datasheet, PDF (340/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–76
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
rx_enapatternalign signal. If you create a rising edge on the
rx_enapatternalign signal before the word alignment pattern is received across
clock cycles m, m + 1, and m + 2, the word aligner re-aligns to the new word
boundary, causing both the rx_syncstatus and rx_patterndetect signals to go
high for one parallel clock cycle.
Figure 1–60. Bit-Slip Mode in 8-Bit PMA-PCS Interface Mode
rx_dataout[7:0]
n
11110110
F6
n+1
00101000
28
m
0110xxxx
6x
m+1
10001111
8F
m+2
xxxx0010
x2
rx_enapatternalign
rx_patterndetect
rx_syncstatus
Bit-Slip Mode Word Aligner with 8-Bit PMA-PCS Interface Modes
Basic single-width mode with 8-bit PMA-PCS interface width allows the word aligner
to be configured in bit-slip mode. The word aligner operation is controlled by the
input signal rx_bitslip in bit-slip mode. At every rising edge of the rx_bitslip
signal, the bit-slip circuitry slips one bit into the received data stream, effectively
shifting the word boundary by one bit. In bit-slip mode, the word aligner status signal
rx_patterndetect is driven high for one parallel clock cycle when the received
data after bit-slipping matches the 16-bit word alignment pattern programmed in the
ALTGX MegaWizard Plug-In Manager.
You can implement a bit-slip controller in the core fabric that monitors either the
rx_dataout signal and/or the rx_patterndetect signal and controls the
rx_bitslip signal to achieve word alignment.
Figure 1–61 shows an example of the word aligner configured in bit-slip mode. For
this example, consider that 8'b11110000 is received back-to-back and
16'b0000111100011110 is specified as the word alignment pattern. A rising edge on the
rx_bitslip signal at time n + 1 slips a single bit 0 at the MSB position, forcing the
rx_dataout to 8'b01111000. Another rising edge on the rx_bitslip signal at time
n + 5 forces rx_dataout to 8'b00111100. Another rising edge on the rx_bitslip
signal at time n + 9 forces rx_dataout to 8'b00011110. Another rising edge on the
rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. At this
instance, rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111,
respectively, which matches the specified 16-bit alignment pattern
16'b0000111100011110. This results in the assertion of the rx_patterndetect signal.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation