HD64F2149 Datasheet, PDF (980/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SEDGR—Edge Sense Register
H'FFFF
Timer Connection
Bit
7
6
5
4
3
2
1
0
VEDG HEDG CEDG HFEDG VFEDG PREQF IHI
IVI
Initial value
0
0
0
0
0
0
—^*2
—^*2
Read/Write R/(W)^*1 R/(W)^*1 R/(W)^*1 R/(W)^*1 R/(W)^*1 R/(W)^*1 R
R
IVI signal level
0 The IVI signal is low
1 The IVI signal is high
IHI signal level
0 The IHI signal is low
1 The IHI signal is high
Pre-equalization flag
0 [Clearing condition]
When 0 is written in PREQF after
reading PREQF = 1
1 [Setting condition]
When an IHI signal 2fH modification
condition is detected
VFBACKI edge
0 [Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
1 [Setting condition]
When a rising edge is detected on the VFBACKI pin
HFBACKI edge
0 [Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
1 [Setting condition]
When a rising edge is detected on the HFBACKI pin
CSYNCI edge
0 [Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
1 [Setting condition]
When a rising edge is detected on the CSYNCI pin
HSYNCI edge
0 [Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
1 [Setting condition]
When a rising edge is detected on the HSYNCI pin
VSYNCI edge
0 [Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
1 [Setting condition]
When a rising edge is detected on the VSYNCI pin
Notes: 1. Only 0 can be written, to clear the flags.
2. The initial value is undefined since it depends on the pin states.
946