HD64F2149 Datasheet, PDF (410/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

MSTPCRH Bit 5—Module Stop (MSTP13): Specifies FRT module stop mode.
MSTPCRH
Bit 5
MSTP13 Description
0
FRT module stop mode is cleared
1
FRT module stop mode is set
(Initial value)
MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop
mode.
MSTPCRH
Bit 4
MSTP12 Description
0
8-bit timer channel 0 and 1 module stop mode is cleared
1
8-bit timer channel 0 and 1 module stop mode is set
(Initial value)
MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer
connection module stop mode.
MSTPCRH
Bit 0
MSTP8 Description
0
8-bit timer channel X and Y and timer connection module stop mode is cleared
1
8-bit timer channel X and Y and timer connection module stop mode is (Initial value)
set
13.3 Operation
13.3.1 PWM Decoding (PDC Signal Generation)
The timer connection facility and TMRX can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMRX is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the compare-match signal B timing after TCNT is
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