HD64F2149 Datasheet, PDF (901/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

HICR2—Host Interface Control Register 2
H'FE42
HIF (LPC)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
GA20
0
R
—
6
LRST
0
R/(W)*
—
5
SDWN
0
R/(W)*
—
4
ABRT
0
R/(W)*
—
3
IBFIE3
0
R/W
—
2
IBFIE2
0
R/W
—
1
IBFIE1
0
R/W
—
0
ERRIE
0
R/W
—
Input data register full interrupt enable 3 to 1/error interrupt enable
IBFIE3 IBFIE2 IBFIE1 ERRI
Description
———
0 Error interrupt requests disabled
———
1 Error interrupt requests enabled
——
0
— Input data register IDR1 receive-complete
interrupt request disabled
——
1
— Input data register IDR1 receive-complete
interrupt request enabled
—
0
— — Input data register IDR2 receive-complete
interrupt request disabled
—
1
— — Input data register IDR2 receive-complete
interrupt request enabled
0
— — — Input data register IDR3 and TWR
receive-complete interrupt requests disabled
1
— — — Input data register IDR3 and TWR
receive-complete interrupt requests enabled
LPC above interrupt flag
0 [Clearing conditions]
• Writing 0 after reading ABRT = 1
• LPC hardware reset (LRESET pin falling edge detection)
• LPC software reset (LRSTB = 1)
• LPC hardware shutdown (SDWNE = 1 and LPCPD falling edge detection)
• LPC software shutdown (SDWNB = 1)
1 [Setting condition]
• LFRAME pin falling edge detection during LPC transfer cycle
LPC shutdown interrupt flag
0 [Clearing conditions]
• Writing 0 after reading SDWN = 1
• LPC hardware reset (LRESET pin falling edge detection)
• LPC software reset (LRSTB = 1)
1 [Setting condition]
• LPCPD pin falling edge detection
LPC reset interrupt flag
0 [Clearing condition]
• Writing 0 after reading LRST = 1
1 [Setting condition]
• LRESET pin falling edge detection
GA20 pin monitor
0 GA20 pin goes to low level
1 GA20 pin goes to high level
Note: * Only 0 can be written to bits 6 to 4, to clear the flags.
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