HD64F2149 Datasheet, PDF (634/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR0 Bit 2—SMI Interrupt Enable 2 (SMIE2): Enables or disables a SMI interrupt
request when OBF2 is set by an ODR2 write.
Bit 2
SMIE2
0
1
Description
SMI interrupt request by OBF2 and SMIE2 is disabled
[Clearing conditions]
• Writing 0 to SMIE2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
[When IEDIR = 0]
SMI interrupt request by setting OBF2 to 1 is enabled
[When IEDIR = 1]
SMI interrupt is requested
[Setting condition]
• Writing 1 after reading SMIE2 = 0
(Initial value)
SIRQCR1 Bit 3—HIRQ11 Interrupt Enable 2 (IRQ11E2): Enables or disables a HIRQ11
interrupt request when OBF2 is set by an ODR2 write.
Bit 3
IRQ11E2
0
1
Description
HIRQ11 interrupt request by OBF2 and IRQ11E2 is disabled
[Clearing conditions]
• Writing 0 to IRQ11E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
[When IEDIR = 0]
HIRQ11 interrupt request by setting OBF2 to 1 is enabled
[When IEDIR = 1]
HIRQ11 interrupt is requested
[Setting condition]
• Writing 1 after reading IRQ11E2 = 0
(Initial value)
600