HD64F2149 Datasheet, PDF (533/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 1—General Call Address Recognition Flag (ADZ): In I²C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1
ADZ
0
1
Description
General call address not recognized
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in ADZ after reading ADZ = 1
3. In master mode
General call address recognized
[Setting condition]
When the general call address is detected in slave receive mode
while FSX = 0 or FS = 0
Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the
receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In
receive mode, after data has been received, the acknowledge data set in this bit is sent to the
transmitting device.
When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
When writing to this bit, acknowledge data that is returned after receiving is rewritten regardless
of the TRS value. The data loaded from receiving device is retained, therefore pay attention when
using bit-manipulation instructions.
Bit 0
ACKB
0
1
Description
Receive mode: 0 is output at acknowledge output timing
(Initial value)
Transmit mode: Indicates that the receiving device has acknowledged the data (signal
is 0)
Receive mode: 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowledged the data
(signal is 1)
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