HD64F2149 Datasheet, PDF (181/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

8-Bit 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Wait states can be inserted.
Bus cycle
T₁
T₂
T₃
ø
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Figure 6.6 Bus Timing for 8-Bit 3-State Access Space
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