HD64F2149 Datasheet, PDF (212/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SAR
Transfer
DAR
Figure 7.6 Memory Mapping in Normal Mode
7.3.6 Repeat Mode
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial address register state specified by the transfer counter and repeat area resumes and transfer
is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts
cannot be requested when DISEL = 0.
Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in
repeat mode.
Table 7.6 Register Information in Repeat Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Function
Transfer source address
Transfer destination address
Holds number of transfers
Transfer count
Not used
178