HD64F2149 Datasheet, PDF (391/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 12.14 shows this operation.
TCNT write cycle by CPU
T₁
T₂
ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.14 Contention between TCNT Write and Increment
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